A transceiver within an Integrated Circuit (IC) plays an important role to enable high speed digital data communications. Transceivers, typically, include transmitter circuitry to transmit signals and receiver circuitry to receive signals. The receiver circuitry may be built with multiple blocks of specialized circuitry, e.g., First-in-First-out (FIFO) registers, deserializers, and phase lock loop (PLL) and clock and data recovery (CDR) circuitry, etc.
A PLL may be used to generate a clock signal with different phases or frequencies based on an input reference clock. The PLL may include a voltage control oscillator (VCO) and a phase detector circuit. The PLL circuit may further include frequency divider circuits for dividing the frequency of an output signal generated by the VCO. Accordingly, the output signal may be analyzed by a phase detector after it has been divided to determine the phase differences. This improves the PLLs function to generate the clock. Two types of frequency dividers include integer frequency dividers and fractional frequency dividers.
A problem with conventional frequency dividers is that it has a fixed divisional factor. Thus, it limits the ability to carry out functions based on different divisional factors. Add-on logic may be used to provide flexibility to conventional frequency dividers such that they are not fixed to a specific division factor but the drawbacks of the add-on logic is that it may reduce the speed of carrying out frequency divisional. Furthermore, the add-on logic is known to increase power consumption and area utilization within the IC.
It is within this context that the embodiments described herein arise.